How could SK Hynix's new memory standards affect Nvidia's AI accelerator platforms?
New memory standards could offer Nvidia new design options for AI accelerators The finalization of the High-Bandwidth Flash (HBF) standard and the disclosure of 3D Stacked DRAM architecture present Nvidia with new memory options for its AI accelerators. HBF is designed specifically for AI inference, offering ten times the capacity of HBM while delivering half its bandwidth, which addresses the growing data volume needs of AI workloads. Furthermore, SK Hynix's 3D Stacked DRAM eliminates the need for a silicon interposer, allowing DRAM dies to bond directly onto the processor die, a shift that requires co-design partnerships but offers higher bandwidth and lower power per bit. These new, standardized tiers could allow Nvidia to tailor its chip designs to specific workload characteristics, such as inference versus training.
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SK Hynix formally disclosed a next-generation memory roadmap, detailing a 3D Stacked DRAM architecture that bonds DRAM dies directly onto the processor die using Through-Silicon Via interconnects, targeting mass production in 2028. The company also advanced its High-Bandwidth Flash format, whose Open Compute Project technical specification is finalized to target a complete standard in January 2027 with the Google Tenstorrent HBF consortium.
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SK Hynix's new memory tiers, including HBF and 3D Stacked DRAM, provide alternative architectural solutions for AI workloads. HBF is designed for AI inference, offering ten times the capacity of HBM, while 3D Stacked DRAM enables higher bandwidth and lower power per bit by eliminating the lateral silicon interposer used in current HBM designs. These options could influence how Nvidia designs its next-generation AI accelerator platforms.
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The facts so far
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- The High-Bandwidth Flash (HBF) standard is targeting complete finalization in January 2027.techtimes.com
- HBF delivers half HBM bandwidth but ten times the capacity, making it suitable for AI inference.techtimes.com
- SK Hynix's 3D Stacked DRAM targets mass production in 2028.techtimes.com
- 3D Stacked DRAM eliminates the silicon interposer, allowing DRAM dies to bond directly onto the processor die.techtimes.com
Why it matters
Nvidia relies heavily on advanced memory solutions, such as HBM, to power its AI accelerator platforms. The memory industry is undergoing a fundamental restructuring, moving beyond incremental HBM improvements to introduce new tiers like HBF and 3D Stacked DRAM. These changes are driven by the massive data volume generated by AI workloads, which SK Hynix projects will cause AI infrastructure performance requirements to grow 19 to 20 times by 2030.
This shift means that memory is becoming a co-designed component rather than an interchangeable commodity. For Nvidia, this presents a strategic opportunity to integrate these new, highly specialized memory solutions into its chip designs, potentially optimizing performance for specific workloads like inference, while also introducing new competitive dynamics from other memory suppliers.
What we don't know yet
- How quickly will the industry adopt the new HBF and 3D Stacked DRAM standards?
- What specific architectural changes will Nvidia make to its chips to leverage 3D Stacked DRAM?
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